P912XDP512F0MFVR datasheet(634/1350 Pages) FREESCALE

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Chapter 17 Memory Mapping Control (S12XMMCV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

634

Freescale Semiconductor

Expansion of the BDM Local Address Map

PPAGE, RPAGE, and EPAGE registers are also used for the expansion of the BDM local address to the

global address. These registers can be read and written by the BDM.

The BDM expansion scheme is the same as the CPU expansion scheme.

17.4.2.2

Global Addresses Based on the Global Page

CPU Global Addresses Based on the Global Page

The seven global page index bits allow access to the full 8 Mbyte address map that can be accessed with

23 address bits. This provides an alternative way to access all of the various pages of FLASH, RAM and

EEPROM as well as additional external memory.

The GPAGE Register is used only when the CPU is executing a global instruction (see Section 1.3.2.3,

“Global Page Index Register (GPAGE)”). The generated global address is the result of concatenation of

the CPU local address [15:0] with the GPAGE register [22:16] (see Figure 1-7).

BDM Global Addresses Based on the Global Page

The seven BDMGPR Global Page index bits allow access to the full 8 Mbyte address map that can be

accessed with 23 address bits. This provides an alternative way to access all of the various pages of

FLASH, RAM and EEPROM as well as additional external memory.

The BDM global page index register (BDMGPR) is used only in the case the CPU is executing a ﬁrmware

command which uses a global instruction (like GLDD, GSTD) or by a BDM hardware command (like

WRITE_W, WRITE_BYTE, READ_W, READ_BYTE). See the BDM Block Guide for further details.

The generated global address is a result of concatenation of the BDM local address with the BDMGPR

BDMGPR register [22:16] in the case of a ﬁrmware command (see Figure 1-22).

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