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P912XDP512F0MFVR 数据表(PDF) 658 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MFVR 数据表(HTML) 658 Page - Freescale Semiconductor, Inc |
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658 / 1350 page  Chapter 18 Memory Mapping Control (S12XMMCV3) MC9S12XDP512 Data Sheet, Rev. 2.17 658 Freescale Semiconductor Table 18-5. MMCCTL0 Field Descriptions Field Description 3–0 CS[3:0]E Chip Select Enables — Each of these bits enables one of the external chip selects CS3, CS2, CS1, and CS0 outputs which are asserted during accesses to specific external addresses. The associated global address ranges are shown in Table 18-6 and Table 18-21 and Figure 18-21. Chip selects are only active if enabled in normal expanded mode, Emulation expanded mode and special test mode. The function disabled in all other operating modes. 0 Chip select is disabled 1 Chip select is enabled Table 18-6. Chip Select Signals Global Address Range Asserted Signal 0x00_0800–0x0F_FFFF CS3 0x10_0000–0x1F_FFFF CS2 0x20_0000–0x3F_FFFF CS1 0x40_0000–0x7F_FFFF CS01 1 When the internal NVM is enabled (see ROMON in Section 18.3.2.5, “MMC Control Register (MMCCTL1)) the CS0 is not asserted in the space occupied by this on-chip memory block. |
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