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P912XDP512F0MFVR 数据表(PDF) 686 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MFVR 数据表(HTML) 686 Page - Freescale Semiconductor, Inc |
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686 / 1350 page  Chapter 18 Memory Mapping Control (S12XMMCV3) MC9S12XDP512 Data Sheet, Rev. 2.17 686 Freescale Semiconductor Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in emulation modes. A summary of PRR accesses: • An aligned word access to a PRR will take 2 bus cycles. • A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the misaligned word access is not a PRR, the access will take only 3 cycles. • A byte access to a PRR will take 2 cycles. Table 18-24. PRR Listing PRR Name PRR Local Address PRR Location PORTA 0x0000 PIM PORTB 0x0001 PIM DDRA 0x0002 PIM DDRB 0x0003 PIM PORTC 0x0004 PIM PORTD 0x0005 PIM DDRC 0x0006 PIM DDRD 0x0007 PIM PORTE 0x0008 PIM DDRE 0x0009 PIM MMCCTL0 0x000A MMC MODE 0x000B MMC PUCR 0x000C PIM RDRIV 0x000D PIM EBICTL0 0x000E EBI EBICTL1 0x000F EBI Reserved 0x0012 MMC MMCCTL1 0x0013 MMC ECLKCTL 0x001C PIM Reserved 0x001D PIM PORTK 0x0032 PIM DDRK 0x0033 PIM |
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