P912XDP512F0MFVR datasheet(769/1350 Pages) FREESCALE

769 / 1350 page

Chapter 20 S12X Debug (S12XDBGV3) Module

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

769

The trace buffer is visible through a 2-byte window in the register address map and can be read out using

standard 16-bit word reads.

Figure 20-22. S12XDBG Overview

20.4.2

Comparator Modes

The S12XDBG contains four comparators, A, B, C, and D. Each comparator can be conﬁgured to monitor

either S12XCPU or XGATE buses using the SRC bit in the corresponding comparator control register.

Each comparator compares the selected address bus with the address stored in DBGXAH, DBGXAM, and

DBGXAL. Furthermore, comparators A and C also compare the data buses to the data stored in DBGXDH,

DBGXDL and allow masking of individual data bus bits.

All comparators are disabled in BDM and during BDM accesses.

The comparator match control logic (see Figure 20-22) conﬁgures comparators to monitor the buses for

an exact address or an address range, whereby either an access inside or outside the speciﬁed range

generates a match condition. The comparator conﬁguration is controlled by the control register contents

and the range control by the DBGC2 contents.

On a match a trigger can initiate a transition to another state sequencer state (see Section 20.4.3”). The

comparator control register also allows the type of access to be included in the comparison through the use

of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled

for the associated comparator and the RW bit selects either a read or write access for a valid match.

Similarly the SZE and SZ bits allows the size of access (word or byte) to be considered in the compare.

Only comparators B and D feature SZE and SZ.

The TAG bit in each comparator control register is used to determine the triggering condition. By setting

TAG, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs

S12XCPU BUS

TRACE BUFFER

TRIGGER

EXTERNAL TAGHI / TAGLO

MATCH0

STATE

XGATE BUS

COMPARATOR B

COMPARATOR C

COMPARATOR D

COMPARATOR A

STATE SEQUENCER

MATCH1

MATCH2

MATCH3

TRACE

READ TRACE DATA (DBG READ DATA BUS)

CONTROL

SECURE

BREAKPOINT REQUESTS

XGATE S/W BREAKPOINT REQUEST

TRIGGER

TAG &

TRIGGER

CONTROL

LOGIC

P912XDP512F0MFVR 数据表(PDF) 769 Page - Freescale Semiconductor, Inc

P912XDP512F0MFVR 数据表(HTML) 769 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

P912XDP512F0MFVR 数据表(PDF) 769 Page - Freescale Semiconductor, Inc

P912XDP512F0MFVR 数据表(HTML) 769 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载