P912XDP512F0MFVR datasheet(788/1350 Pages) FREESCALE

部件名	P912XDP512F0MFVR

功能描述	Covers, S12XD, S12XB & S12XA Families

PDF	1350 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

标志

788 / 1350 page

Chapter 21 External Bus Interface (S12XEBIV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

788

Freescale Semiconductor

21.1.3

Block Diagram

Figure 21-1 is a block diagram of the XEBI with all related I/O signals.

Figure 21-1. XEBI Block Diagram

21.2

External Signal Description

The user is advised to refer to the SoC section for port configuration and location of external bus signals.

NOTE

The following external bus related signals are described in other sections:

CS2, CS1, CS0 (chip selects) — S12X_MMC section

ECLK, ECLKX2 (free-running clocks) — PIM section

TAGHI, TAGLO (tag inputs) — PIM section, S12X_DBG section

Table 21-1 outlines the pin names and gives a brief description of their function. Refer to the SoC section

and PIM section for reset states of these pins and associated pull-ups or pull-downs.

XEBI

ADDR[22:0]

DATA[15:0]

LSTRB

R/W

UDS

LDS

EWAIT

ACC[2:0]

IQSTAT[3:0]

IVD[15:0]

P912XDP512F0MFVR 数据表(PDF) 788 Page - Freescale Semiconductor, Inc