P912XDP512F0MFVR datasheet(838/1350 Pages) FREESCALE

838 / 1350 page

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

838

Freescale Semiconductor

22.3.2.15 Port K Data Register (PORTK)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data source is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

22.3.2.16 Port K Data Direction Register (DDRK)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data are read from this register.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

This register controls the data direction for port K. When Port K is operating as a general purpose I/O port,

DDRK determines whether each pin is an input or output. A logic level “1” causes the associated port pin

to be an output and a logic level “0” causes the associated pin to be a high-impedance input.

76543210

PK7

PK6

PK5

PK4

PK3

PK2

PK1

PK0

Alt.

Func.

ROMCTL

EWAIT

ADDR22

mux

NOACC

ADDR21

ADDR20

ADDR19

mux

IQSTAT3

ADDR18

mux

IQSTAT2

ADDR17

mux

IQSTAT1

ADDR16

mux

IQSTAT0

Reset

00000000

Figure 22-17. Port K Data Register (PORTK)

Table 22-19. PORTK Field Descriptions

Field

Description

7–0

PK[7:0]

Port K — Port K pins 7–0 are associated with external bus control signals and internal memory expansion

emulation pins. These include ADDR22-ADDR16, No-Access (NOACC), External Wait (EWAIT) and instruction

pipe signals IQSTAT3-IQSTAT0. Bits 6-0 carry the external addresses in all expanded modes. In emulation or

special test mode with internal visibility enabled the address is multiplexed with the alternate functions NOACC

and IQSTAT on the respective pins. In single-chip modes the port pins can be used as general-purpose I/O. If

the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port

76543210

DDRK7

DDRK6

DDRK5

DDRK4

DDRK3

DDRK2

DDRK1

DDRK0

Reset

00000000

Figure 22-18. Port K Data Direction Register (DDRK)

P912XDP512F0MFVR 数据表(PDF) 838 Page - Freescale Semiconductor, Inc

P912XDP512F0MFVR 数据表(HTML) 838 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载