P912XDP512F0MFVR datasheet(106/1350 Pages) FREESCALE

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Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.17

106

Freescale Semiconductor

There are four different scenarios for the CRG to restart the MCU from wait mode:

•

External reset

•

Clock monitor reset

•

COP reset

•

Any interrupt

If the MCU gets an external reset or COP reset during wait mode active, the CRG asynchronously restores

all conﬁguration bits in the register space to its default settings and starts the reset generator. After

completing the reset sequence processing begins by fetching the normal or COP reset vector. Wait mode

is left and the MCU is in run mode again.

If the clock monitor is enabled (CME = 1) the MCU is able to leave wait mode when loss of

oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG

generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same

compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the

SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE = 1). After generating the

interrupt the CRG enters self-clock mode and starts the clock quality checker (Section 2.4.1.4, “Clock

Quality Checker”). Then the MCU continues with normal operation.If the SCM interrupt is blocked by

SCMIE = 0, the SCMIF ﬂag will be asserted and clock quality checks will be performed but the MCU will

not wake-up from wait-mode.

If any other interrupt source (e.g., RTI) triggers exit from wait mode, the MCU immediately continues with

normal operation. If the PLL has been powered-down during wait mode, the PLLSEL bit is cleared and

the MCU runs on OSCCLK after leaving wait mode. The software must manually set the PLLSEL bit

again, in order to switch system and core clocks to the PLLCLK.

If wait mode is entered from self-clock mode the CRG will continue to check the clock quality until clock

check is successful. The PLL and voltage regulator (VREG) will remain enabled.

Table 2-12 summarizes the outcome of a clock loss while in wait mode.

2.4.3.3

System Stop Mode

All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE, and PSTP bit. The

oscillator is disabled in STOP mode unless the PSTP bit is set. All counters and dividers remain frozen but

do not initialize. If the PRE or PCE bits are set, the RTI or COP continues to run in pseudo stop mode. In

addition to disabling system and core clocks the CRG requests other functional units of the MCU (e.g.,

voltage-regulator) to enter their individual power saving modes (if available). This is the main difference

between pseudo stop mode and wait mode.

If the PLLSEL bit is still set when entering stop mode, the CRG will switch the system and core clocks to

OSCCLK by clearing the PLLSEL bit. Then the CRG disables the PLL, disables the core clock and ﬁnally

disables the remaining system clocks. As soon as all clocks are switched off, stop mode is active.

If pseudo stop mode (PSTP = 1) is entered from self-clock mode, the CRG will continue to check the clock

quality until clock check is successful. The PLL and the voltage regulator (VREG) will remain enabled. If

full stop mode (PSTP = 0) is entered from self-clock mode, an ongoing clock quality check will be

stopped. A complete timeout window check will be started when stop mode is left again.

Wake-up from stop mode also depends on the setting of the PSTP bit.

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