P912XDP512F0MFVR datasheet(168/1350 Pages) FREESCALE

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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3)

MC9S12XDP512 Data Sheet, Rev. 2.17

168

Freescale Semiconductor

5.3.2.3

ATD Control Register 2 (ATDCTL2)

This register controls power down, interrupt and external trigger. Writes to this register will abort current

conversion sequence but will not start a new sequence.

Read: Anytime

Write: Anytime

76543210

ADPU

AFFC

AWAI

ETRIGLE

ETRIGP

ETRIGE

ASCIE

ASCIF

Reset

00000000

= Unimplemented or Reserved

Figure 5-5. ATD Control Register 2 (ATDCTL2)

Table 5-5. ATDCTL2 Field Descriptions

Field

Description

ADPU

ATD Power Up — This bit provides on/off control over the ATD block allowing reduced MCU power

consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time

period after ADPU bit is enabled.

0 Power down ATD

1 Normal ATD functionality

AFFC

ATD Fast Flag Clear All

0 ATD ﬂag clearing operates normally (read the status register ATDSTAT1 before reading the result register to

clear the associate CCF ﬂag).

1 Changes all ATD conversion complete ﬂags to a fast clear sequence. Any access to a result register will

cause the associate CCF ﬂag to clear automatically.

AWAI

ATD Power Down in Wait Mode — When entering wait mode this bit provides on/off control over the ATD block

allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires

a recovery time period after exit from Wait mode.

0 ATD continues to run in Wait mode

1 Halt conversion and power down ATD during wait mode

After exiting wait mode with an interrupt conversion will resume. But due to the recovery time the result of

this conversion should be ignored.

ETRIGLE

External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See

Table 5-6 for details.

ETRIGP

External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 5-6 for

details.

ETRIGE

External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of

the ETRIG3–0 inputs as described in Table 5-4. If external trigger source is one of the AD channels, the digital

input buffer of this channel is enabled. The external trigger allows to synchronize sample and ATD conversions

processes with external events.

0 Disable external trigger

1 Enable external trigger

Note: If using one of the AD channel as external trigger (ETRIGSEL = 0) the conversion results for this channel

have no meaning while external trigger mode is enabled.

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