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P912XDP512F0MFVR 数据表(PDF) 191 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MFVR 数据表(HTML) 191 Page - Freescale Semiconductor, Inc |
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191 / 1350 page  Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 191 4 XGSS XGATE Single Step — This bit forces the execution of a single instruction if the XGATE is in DEBUG Mode and no software error has occurred (XGSWEIF cleared). Read: 0 No single step in progress 1 Single step in progress Write 0 No effect 1 Execute a single RISC instruction Note: Invoking a Single Step will cause the XGATE to temporarily leave Debug Mode until the instruction has been executed. 3 XGFACT Fake XGATE Activity — This bit forces the XGATE to flag activity to the MCU even when it is idle. When it is set the MCU will never enter system stop mode which assures that peripheral modules will be clocked during XGATE idle periods Read: 0 XGATE will only flag activity if it is not idle or in debug mode. 1 XGATE will always signal activity to the MCU. Write: 0 Only flag activity if not idle or in debug mode. 1 Always signal XGATE activity. 1 XGSWEIF XGATE Software Error Interrupt Flag — This bit signals a pending Software Error Interrupt. It is set if the RISC core detects an error condition (see Section 6.4.5, “Software Error Detection”). The RISC core is stopped while this bit is set. Clearing this bit will terminate the current thread and cause the XGATE to become idle. Read: 0 Software Error Interrupt is not pending 1 Software Error Interrupt is pending if XGIE is set Write: 0 No effect 1 Clears the XGSWEIF bit 0 XGIE XGATE Interrupt Enable — This bit acts as a global interrupt enable for the XGATE module Read: 0 All XGATE interrupts disabled 1 All XGATE interrupts enabled Write: 0 Disable all XGATE interrupts 1 Enable all XGATE interrupts Table 6-1. XGMCTL Field Descriptions (Sheet 3 of 3) Field Description |
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