MU9C8328A Ethernet Interface

Rev. 0.8 Draft

10

Step

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

A(2–0)

0H

5H

5H

5H

5H

5H

5H

5H

5H

5H

5H

5H

5H

5H

5H

5H

5H

5H

5H

5H

7H

5H

5H

5H

5H

5H

5H

5H

7H

7H

7H

7H

5H

5H

5H

5H

0H

/WE

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

Mnemonic

TCO_DS

TCO_CT

TCO_PA

SFF

TCO_PA

SFF

TCO_CT

SBR

TCO_CT

TCO_SC

SPD_MR1

SPD_CR

SFR

TCO_CT

SPD_MR1

TCO_SC

SPD_CR

TCO_SC

SPS_HM

D(15–0)

C000H

0000H

0228H

FFFFH

0200H

0000H

0208H

0000H

0700H

0208H

0001H

0700H

0200H

0000H

0619H

0200H

8111H

0210H

0000H

0108H

FFF0H

0100H

0618H

0200H

8041H

0108H

0210H

1C04H

FFF0H

FFFFH

FFFFH

FFFFH

0100H

0210H

3808H

0005H

290BH

Comments

Pass all frames during initialization

Command Read to reset LANCAM state machines

Selects all Device Select registers

Selects all LANCAMs

Selects all Control registers

Resets all memory locations

Selects first Page Address register

Writes first Page Address value

Sets Full flag on first LANCAM

Selects second Page Address register

Writes second Page Address value

Sets Full flag on second LANCAM

Selects all Control registers

Resets all Full flags

Select Background Register set

TCO CT

48RAM, 16CAM, MR1, Enhanced mode

Select Segment Control register

Set Read and Write to segment 0

Set Persistent Destination to Mask Register 1

Setup Time Stamp in lowest 8 bits of segment 0

Set Persistent Destination to Comparand register

Select Foreground Register set

Select Command register

48CAM, 16RAM, No Mask, Enhanced mode

Set Persistent Destination to Mask Register 1

Select Segment Control register

Set to write Segments 0, 1, 2, and 3

Write to Segment 0 of MR1

Write to Segment 1 of MR1

Write to Segment 2 of MR1

Write to Segment 3 of MR1

Set Persistent Destination to Comparand register

Select Segment Control register

Write Segments 1–3, Read Segment 0

Set Persistent source to Highest match

Enable filter, Negative filter on DA, enable learn

Table 3: LANCAM Initialization Code

the Persistent destination to the Comparand register as

shown in Table 3. If only one LANCAM is used, Table 3

would be modified to replace steps 9 through 14 with a

TCO DS (0228H) followed by a 0000H.

Enabling Network Activity

After the LANCAMs have been initialized, the MU9C8328A

is enabled to begin processing network traffic by setting

bit 13 (NETEN) in its Control register to a 1 along with the

desired filtering actions and interrupt enables.

Responding to Interrupts

Depending on the filtering or error interrupt conditions set

in the MU9C8328A Control register, the /INT line will assert

at the end of the frame SA field. The host can then read the

MU9C8328A Status register to determine the cause of the

interrupt, whereupon the Status register is reset. If there

was a DA match interrupt and read associated data was

set, then the associated data segment stored in the

LANCAM at the same location that matched the frame’s

DA can be read out of the Associated Data register (03H).

APPLICATIONS

Continued