MU9C8328A Ethernet Interface

Rev. 0.8 Draft

9

Connections

Connection diagrams are shown in Figures 2, 3, and 4 for

National’s SONIC, AMD’s MACE, and Motorola’s

QUICC Ethernet controller chips. Other controller chips

that provide a serial NRZ received data port and clock

can also be used in similar fashions. The /NETRDY line

is provided for controller chips that output data on the

received data line while transmitting. If /NETRDY is

deasserted, the internal network state machine will safely

complete any current activity and then wait until

/NETRDY is asserted again before parsing another frame.

If the controller chip does not output data on the received

data line while transmitting, /NETRDY may be tied to

ground, and the MU9C8328As valid clock detector will

determine when it is time to start parsing a frame.

Initialization of the LANCAM

Before using, the MUSIC LANCAMs need to be configured

for the number of LANCAMs in a daisy chain and for the

filtering conditions in the Control and Segment Control

registers. Before configuring the LANCAMs, bit 13 in the

MU9C8328A Control register needs to be set to 0, to turn off

network filtering. Table 3 shows the steps for configuring two

LANCAMs in a daisy chain. The routine selects register 05H

in the MU9C8328A, which sends Command Write cycles to

the LANCAM. The sequence shown resets the LANCAMs,

sets the Page address for both LANCAMs in the daisy chain,

then sets the Control and Segment Control registers. If a Mask

register were needed, then the sequence would be modified to

set the Persistent destination to MR1 or MR2, use MU9C8328A

register 07H to write data into the Mask register, change the

final Control register value to 8051H or 8061H instead of 8041H

to invoke MR1 or MR2 during compares, and then resetting

APPLICATIONS

Figure 4: Motorola’s QUICC™ Connection Diagram

Figure 2: AMD’s MACE™ Connection Diagram

Figure 3: National’s SONIC™ Connection Diagram

LANCAM

MU9C8328A

/E

/EC

/MF

/FF

DQ(15-0)

/CM

/W

D(15-0)

READY

/CS

/WE

/RESET

A(3-0)

SERCLK

SERDAT

/REJECT

/INT

SYSCLK

/AS

M C 68160

EE ST

MC68360

QUICC

RX

RXD

/RRJCT

RCLK

RCLK

RENA

RENA

/NETRDY

/E

/EC

/MF

/FF

/CM

/W

LANCAM

MU9C8328A

AM79C940

SRDCLK

SRD

/EAM/R

/E

/EC

/MF

/FF

DQ(15-0)

/CM

/W

D(15-0)

READY

/CS

/WE

/RESET

A(3-0)

SERCLK

SERDAT

/REJECT

/INT

SYSCLK

/AS

TXEN

/NETRDY

/E

/EC

/MF

/FF

/CM

/W

LANCAM

MU9C8328A

DP83932

RXCo

RXDo

/PREJ

/E

/EC

/MF

/FF

DQ(15-0)

/CM

/W

D(15-0)

READY

/CS

/WE

/RESET

A(3-0)

SERCLK

SERDAT

/REJECT

/INT

SYSCLK

/AS

TXE

/NETRDY

/E

/EC

/MF

/FF

/CM

/W