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MU9C8328A-RDI 数据表(PDF) 6 Page - MUSIC Semiconductors |
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MU9C8328A-RDI 数据表(HTML) 6 Page - MUSIC Semiconductors |
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6 / 16 page  MU9C8328A Ethernet Interface Rev. 0.8 Draft 6 FUNCTIONAL DESCRIPTION Continued Table 1: Address Decode Figure 1: Typical Network Filtering A(3–0) /WE Resource Selected Action 0H L Control register Write 0H H Control register Read 1H L Reserved 1H H Status Register Read 2H L Learn Op-Code Register Write 2H H Learn Op-Code Register Read 3H L Reserved 3H H Associated Data Register Read 4H L LANCAM Command Cycle with /EC LOW Write 4H H LANCAM Command Cycle with /EC LOW Read 5H L LANCAM Command Cycle with /EC HIGH Write 5H H LANCAM Command Cycle with /EC HIGH Read 6H L LANCAM Data Cycle with /EC LOW Write 6H H LANCAM Data Cycle with /EC LOW Read 7H L LANCAM Data Cycle with /EC HIGH Write 7H H LANCAM Data Cycle with /EC HIGH Read 8H L Update Op-Code Register Write 8H H Update Op-Code Register Read 9H L Purge Op-Code Register Write 9H H Purge Op-Code Register Read AH L Time stamp Register Write AH H Time stamp Register Read Preamble SFD DA1 SA2 Data Length/Type SERDAT DA2 DA3 SA1 SA3 /E /W /CM /EC /MF /REJECT /INT DA Match Found SA No-Match/Learn |
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