M95M01-RMW6P datasheet(10/39 Pages) STMICROELECTRONICS

10 / 39 page

Connecting to the SPI bus

M95M01-R

10/39

Connecting to the SPI bus

These devices are fully compatible with the SPI protocol.

All instructions, addresses and input data bytes are shifted in to the device, most significant

bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)

after Chip Select (S) goes Low.

All output data bytes are shifted out of the device, most significant bit first. The Serial Data

Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction

(such as the Read from Memory Array and Read Status Register instructions) have been

clocked into the device.

Figure 3.

Bus master and memory devices on the SPI bus

The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

Figure 3 shows an example of three memory devices connected to an MCU, on an SPI bus.

Only one device is selected at a time, so only one device drives the Serial Data Output (Q)

line at a time, the other devices are high impedance.

The pull-up resistor R (represented in Figure 3) ensures that no device is selected if the Bus

Master leaves the S line in the high impedance state.

In applications where the Bus Master might enter a state where all inputs/outputs SPI lines

are in high impedance at the same time (for example, if the Bus Master is reset during the

transmission of an instruction), the clock line (C) must be connected to an external pull-

down resistor so that, if all inputs/outputs become high impedance, the C line is pulled Low

(while the S line is pulled High). This ensures that S and C do not become High at the same

time, and so, that the tSHCH requirement is met.

AI12836b

SPI Bus Master

SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3

CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

HOLD

VCC

VSS

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