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LP3958TL 数据表(PDF) 21 Page - National Semiconductor (TI) |
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LP3958TL 数据表(HTML) 21 Page - National Semiconductor (TI) |
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21 / 28 page ![]() I 2C Compatible Interface (Continued) 20175554 I 2C Timing Diagram I 2C TIMING PARAMETERS (V DD1,2 = 3.0 to 4.5V, VDDIO = 1.8V to VDD1,2) Symbol Parameter Limit Units Min Max 1 Hold Time (repeated) START Condition 0.6 µs 2 Clock Low Time 1.3 µs 3 Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time (Output direction, delay generated by LP3958) 300 900 ns 5 Data Hold Time (Input direction, delay generated by Master) 0 900 ns 6 Data Setup Time 100 ns 7 Rise Time of SDA and SCL 20+0.1C b 300 ns 8 Fall Time of SDA and SCL 15+0.1C b 300 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.3 µs C b Capacitive Load for Each Bus Line 10 200 pF NOTE: Data guaranteed by design www.national.com 21 |
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