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Figure 2 shows a typical server-based design, where the

Root Complex provides a PCI Express link that needs to

be expanded into a larger number of smaller ports for a

variety of I/O functions, each with different bandwidth

requirements.

In this example, the ExpressLane PEX 8533 would

typically have an 8-lane upstream port, and as many as 5

downstream ports. The downstream ports can be of

differing widths if required.

Peer-to-Peer & Backplane Usage

The PEX 8533 is also suitable for peer-to-peer

applications such as switch fabrics and backplanes.

Figure 3 represents a backplane where the device

provides peer-to-peer data exchange for a large number

of line cards where the CPU/Host plays the management

role.

Figure 3. Peer-to-Peer/Backplane Usage

Graphics Fan-out Switch

High resolution 3D graphics applications can take full

advantage of the PEX 8533 three port configuration.

Applications such as dual graphics, high resolution

scientific use, and image processing can benefit from

the performance of the PEX 8533 switch. Figure 4

illustrates use of the device in a dual graphics

application while supporting PCI port expansion through

another PLX PCIe switch. The upstream x16 port links

to the Root Complex and the two downstream ports

connect to the Graphics modules. The peer-to-peer

support of the PEX 8533 allows the two GPU modules

to communicate with each other for maximum

performance. Figure 4 also illustrates use of PCIe

bridges to connect to PCI and PCI-X busses.

Figure 4. Dual Graphics

Redundant Switch Fabric

The PEX 8533 can be used in redundant switch fabrics

for high availability applications. In the example shown

in Figure 5, the PEX 8533 is used in conjunction with

the PEX 8518 switch that offers non-transparent

bridging (NTB). The PEX 8533 provides high

performance non-blocking switching while the PEX

8518s keep the two fabrics and hosts isolated.

Figure 5. Blade Server

The number of ports and port widths can be configured

as needed. This example assumes a x8 link to each CPU

blade and a x8 link to each I/O blade.