PLX Confidential

Flexible & Versatile PCI Express™ Switch

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Features

PEX 8533 General Features

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32-lane PCI Express switch

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Integrated SerDes

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Up to six configurable ports

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35mm x 35mm, 680 pin PBGA package

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Pin Compatible with PEX 8532

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Typical Power: 3.3 Watts

PEX 8533 Key Features

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Standards Compliant

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PCI Express Base Specification, r1.1

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PCI SHPC Specification, r1.0

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High Performance

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Cut-through with 120ns packet latency

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Max Payload Size of 1024 Bytes

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Non-blocking switch fabric

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Full line rate on all ports

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Flexible Configuration

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Six highly flexible and configurable ports

(x1, x2, x4, x8, or x16)

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Configurable with strapping pins,

EEPROM, I

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Lane and polarity reversal

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PCI Express Power Management

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Link power management states: L0, L0s,

L1, L2/L3 Ready, and L3

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Device states: D0 and D3hot

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Quality of Service (QoS)

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Eight Traffic Classes per port

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Round robin and weighted RR port

arbitration

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Reliability, Availability, Serviceability

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3 Standard Hot-Plug Controllers

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Upstream port as hot-plug client

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Transaction Layer end-to-end CRC

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Poison bit

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INTA & FATAL ERROR signal support

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Advanced Error Reporting in addition to

PCIe baseline error reporting

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Port Status bits and GPO available

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Per port performance monitoring

• Average packet size, number of

packets, CRC errors

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JTAG boundary scan

Multi-Purpose, Feature Rich PCI Express ExpressLane™ Switch

The ExpressLane

capability conforming to the latest revision of the PCIe Base specification.

This device enables users to add scalable high bandwidth, non-blocking

interconnects to a wide variety of applications including servers, storage

systems, communications platforms, blade servers, and embedded-control

products. The PEX 8533 is well suited for fan-out, aggregation, peer-to-

peer, backplane, and switch fabric applications.

Highly Flexible Port Configurations

The ExpressLane

maximum of 6 ports that can be configured to any legal width from x1 to

x16, in any combination to support your specific bandwidth needs. The ports

can be symmetric (each port having the same lane width) or asymmetric

(ports having different lane widths). Any of the ports can be designated as

the upstream port, which can be changed dynamically.

High Performance

The ExpressLane

with a latency of 115ns (x8 to x8). This, combined with large packet

memory (256 to 1024 byte maximum payload size) and non-blocking

internal switch architecture, provide full line rate on its ports for

performance hungry applications such as storage servers or storage switch

fabrics.

End-to-End Packet Integrity

The ExpressLane

protection (ECRC) and Poison bit support to enable designs that require

guaranteed error-free packets.

Configuration Flexibility

The ExpressLane

operations. The device can be configured through strapping pins, I

interface, CPU configuration cycles, or an optional serial EEPROM. This

allows for easy debug during the development phase, performance

monitoring during the operation phase, and driver or software upgrade.

Interoperability

The ExpressLane

PCI-SIG specification. Additionally, it supports auto-negotiation, lane

reversal, and polarity reversal. The PEX 8533 also undergoes thorough

Interoperability testing in PLX’s Interoperability Lab.

Low Power with Granular SerDes Control

The ExpressLane

compliant with the PCI Express power management specification. In

addition, the SerDes physical links can be turned off when unused for even

lower power.

PEX 8533

Version 1.2 2007