Preliminary - PLX Confidential

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

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CPU

Blade

CPU

Blade

Primary

Host

Primary

Host

CPU

Blade

CPU

Blade

CPU

Blade

CPU

Blade

Primary

Host

Primary

Host

Non-Transparent

Port

PEX 8632

PEX 8632

NT

PEX 8632

PEX 8632

NT

CPU

Blade

CPU

Blade

Secondary

Host

Secondary

Host

CPU

Blade

CPU

Blade

CPU

Blade

CPU

Blade

Secondary

Host

Secondary

Host

Figure 2. Non-Transparent Port

Dual-Host & Failover Support

The PEX 8632 product supports a Non-Transparent

(NT) Port, which enables the implementation of multi-

host systems in communications, storage, and blade

server applications. The NT port allows systems to

isolate host memory domains by presenting the

processor subsystem as an endpoint rather than another

memory system. Base

address registers are used to

translate addresses; doorbell

registers are used to send

interrupts

between the

address

domains; and

scratchpad

registers

(accessible

from both

CPUs) allow

inter-processor

communication (see Figure 2).

Dual Cast

The PEX 8632 supports Dual Cast, a feature which

allows for the copying of data (e.g. packets) from one

ingress port to two egress ports allowing for higher

performance in dual-graphics, storage, security, and

redundant applications.

Read Pacing

The Read Pacing feature allows users to throttle the

amount of read requests being made by downstream

devices. When a downstream device requests several

long reads back-to-back, the Root Complex gets tied up

in serving this downstream port. If this port has a narrow

link and is therefore slow in receiving these read packets

from the Root Complex, then other downstream ports

may become starved – thus, impacting performance. The

Read Pacing feature enhances performances by allowing

for the adequate servicing of all downstream devices.

Hot Plug for High Availability

Hot plug capability allows users to replace hardware

modules and perform maintenance without powering

down the system. The PEX 8632 hot plug capability

feature makes it suitable for High Availability (HA)

applications. Three downstream ports include a

Standard Hot Plug Controller. If the PEX 8632 is used in

an application where one or more of its downstream

ports connect to PCI Express slots, each port’s Hot Plug

Controller can be used to manage the hot-plug event of

its associated slot. Every port on the PEX 8632 is

equipped with a hot-plug control/status register to

support hot-plug capability through external logic via the

I

SerDes Power and Signal Management

The PEX 8632 supports software control of the SerDes

outputs to allow optimization of power and signal

strength in a system. The PLX SerDes implementation

supports four levels of power – off, low, typical, and

high. The SerDes block also supports loop-back modes

and advanced reporting of error conditions, which

enables efficient management of the entire system.

Interoperability

The PEX 8632 is designed to be fully compliant with the

PCI Express Base Specification r2.0, and is backwards

compatible to PCI Express Base Specification r1.1 and

r1.0a. Additionally, it supports auto-negotiation, lane

reversal, and polarity reversal. Furthermore, the PEX

8632 is designed for Microsoft Vista compliance. All

PLX switches undergo thorough interoperability testing

in PLX’s Interoperability Lab and compliance testing

at the PCI-SIG plug-fest.

Applications & Usage Models

Suitable for host-centric as well as peer-to-peer traffic

patterns, the PEX 8632 can be configured for a broad

range of form factors and applications.

Host Centric Fan-out

The PEX 8632, with its symmetric or asymmetric lane

configuration capability, allows user-specific tuning to a

variety of host-centric applications. Figure 3 shows a

typical server-based design where the root complex

provides a PCI Express link that needs to be expanded to

a larger number of smaller ports for a variety of I/O

functions. In this example, the PEX 8632 has an 8-lane

upstream port, and four downstream ports using a

combination of x4 and x8 links.

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

PEX 8632

PEX 8632

PEX 8632

PEX 8632

x8

x4

Memory

Memory

Memory

Memory

x8

x8

x4

x8

x4

Endpoint

Endpoint

Endpoint

Endpoint

Chipset

Chipset

Chipset

Chipset

Endpoint

Endpoint

Endpoint

Endpoint

Figure 3. Fan-in/out Usage