Preliminary - PLX Confidential

PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch

Features

PEX 8632 General Features

o

32-lane, 12-port PCIe Gen2 switch

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Integrated 5.0 GT/s SerDes

o

27 x 27mm

o

Typical Power: < 5.5 Watts

PEX 8632 Key Features

o

Standards Compliant

-

PCI Express Base Specification, r2.0

(backwards compatible w/ PCIe r1.0a/1.1)

-

PCI Power Management Spec, r1.2

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Microsoft Vista Compliant

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Supports Access Control Services

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Dynamic link-width control

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Dynamic SerDes speed control

o

High Performance

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Non-blocking switch fabric

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Full line rate on all ports

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Packet Cut-Thru with 145ns max packet

latency (x8 to x8)

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2KB Max Payload Size

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Read Pacing (bandwidth throttling)

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Dual-Cast

o

Flexible Configuration

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Ports configurable as x1, x2, x4, x8, x16

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Registers configurable with strapping

pins, EEPROM, I

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Lane and polarity reversal

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Compatible with PCIe 1.0a PM

o

Dual-Host & Fail-Over Support

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Configurable Non-Transparent port

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Moveable upstream port

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Crosslink port capability

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Quality of Service (QoS)

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Eight traffic classes per port

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Weighted round-robin source

port arbitration

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Reliability, Availability, Serviceability

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3 Hot Plug Ports with native HP Signals

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All ports hot plug capable thru I

(Hot Plug Controller on every port)

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ECRC and Poison bit support

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Data Path parity

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Memory (RAM) Error Correction

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INTA# and FATAL_ERR# signals

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Advanced Error Reporting

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Port Status bits and GPIO available

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Per port error diagnostics

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Performance Monitoring

• Per port payload & header counters

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JTAG AC/DC boundary scan

The ExpressLane

capability enabling users to add scalable high bandwidth, non-blocking

interconnection to a wide variety of applications including servers,

storage systems, and communications platforms. The PEX 8632 is

well suited for fan-out, aggregation, and peer-to-peer applications.

High Performance & Low Packet Latency

The PEX 8632 architecture supports packet cut-thru with a maximum

latency of 145ns (x8 to x8). This, combined with large packet memory and

non-blocking internal switch architecture, provides full line rate on all ports

for performance-hungry applications such as servers and switch fabrics.

The low latency enables applications to achieve high throughput and

performance. In addition to low latency, the device supports a max payload

size of 2048 bytes, enabling the user to achieve even higher throughput.

Data Integrity

The PEX 8632 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction as packets

pass through the switch.

Flexible Register & Port Configuration

The PEX 8632’s 12 ports can be configured to lane widths of x1, x2, x4, x8,

or x16. Flexible buffer allocation, along with the device's flexible packet

flow control, maximizes throughput for applications where more traffic

flows in the downstream, rather than upstream, direction. Any port can be

designated as the upstream port, which can be changed dynamically. The

PEX 8632 also provides

several ways to configure

its registers. The device

can be configured

through strapping pins,

I

software, or an optional

serial EEPROM. This

allows for easy debug

during the development

phase, performance

monitoring during the

operation phase, and

driver or software

upgrade. Figure 1 shows

some of the PEX 8632’s

common port

configurations.

PEX 8632

Version 0.8 2007

Figure 1. Common Port Configurations

PEX 8632

PEX 8632

x4

8 x2

3 x4

PEX 8632

PEX 8632

PEX 8632

PEX 8632

x4

8 x2

3 x4

PEX 8632

PEX 8632

x8

10 x2

PEX 8632

PEX 8632

PEX 8632

PEX 8632

x8

10 x2

PEX 8632

PEX 8632

x8

2 x4

2 x8

PEX 8632

PEX 8632

PEX 8632

PEX 8632

x8

2 x4

2 x8

PEX 8632

PEX 8632

x16

x8

x8

PEX 8632

PEX 8632

PEX 8632

PEX 8632

x16

x8

x8