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DI2CM 数据表(PDF) 4 Page - Digital Core Design |
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DI2CM 数据表(HTML) 4 Page - Digital Core Design |
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4 / 5 page ![]() All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA® devices after Place & Route (all key features have been included): Device Speed grade Logic Cells Fmax STRATIX-II -3 205 380 MHz CYCOLNE-II -6 244 263 MHz MERCURY -5 290 210 MHz STRATIX -5 241 254 MHz CYCLONE -6 241 250 MHz APEX II -7 268 192 MHz APEX20KC -7 268 180 MHz APEX20KE -1 268 160 MHz APEX20K -1 268 122 MHz ACEX1K -1 287 135 MHz FLEX10KE -1 287 140 MHz MAX 2 -3 241 187 MHz MAX 7000AE -5 137 67 MHz MAX 3000A -7 137 49 MHz Core performance in ALTERA® devices The main features of each Digital Core Design I2C compliant cores have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. Design DI2CM 2.1 - - DI2CS 2.1 - - - - DI2CSB 2.1 - - - - - - - I 2C cores summary table |
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