IMPLEMENTATIO N

PERFORMANCE

Figures below show the typical DI2CMS im-

plementations in system with Standard/Fast

and High-speed devices.

The following table gives a survey about the

Core area and performance in the ALTERA®

devices after Place & Route (all key features

have been included):

open drain

open drain

sdai

SCL

SDA

sdao

sclo

scli

DI2CMS

Master

/Slave

device

scl

sda

sclhs

Device

Speed

grade

Logic Cells

STRATIX-II

-3

337

380 MHz

CYCOLNE-II

-6

354

263 MHz

MERCURY

-5

414

210 MHz

STRATIX

-5

370

254 MHz

CYCLONE

-6

370

220 MHz

APEX II

-7

394

192 MHz

APEX20KC

-7

394

150 MHz

APEX20KE

-1

394

120 MHz

APEX20K

-1

394

90 MHz

ACEX1K

-1

411

107 MHz

FLEX10KE

-1

411

107 MHz

MAX 2

-3

291

187 MHz

MAX 7000AE

-5

198

67 MHz

MAX 3000A

-7

198

49 MHz

Core performance in ALTERA® devices

DI2CMS implementation in I

Standard/Fast devices only

open drain

open drain

sdai

SCL

SDA

sdao

sclo

scli

DI2CMS

Master

/Slave

device

scl

sda

sclhs

current-source

pull-up

DI2CMS implementation in I

High-speed devices

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