All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

Fast (up to 400 kb/s)

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S

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I

ver 1.01

OVERVIEW

provides a simple and efficient method of data

transmission over a short distance between

many devices. The DI2CMS core provides an

interface between a microprocessor / micro-

master or slave transmitter/receiver depend-

ing on working mode determined by micro-

processor/microcontroller. The DI2CMS core

incorporates all features required by the latest

tion, arbitration, multi-master systems and

High-speed transmission mode. The DI2CMS

supports all the transmission speed modes.

Built-in timer allows operation from a wide

range of the clk frequencies.

The DI2CMS is a technology independent

VHDL or VERILOG design that can be imple-

mented in a variety of process technologies

and

can be fully customized accordingly to

DI2CMS is delivered with fully automated

testbench

and complete set of tests allow-

ing easy package validation at each stage of

SoC design flow.

KEY FEATURES

Master mode

Master operation

Master transmitter

Master receiver

Support for all transmission speeds

Standard (up to 100 kb/s)

Fast (up to 400 kb/s)

High Speed (up to 3,4 Mb/s)

Arbitration and clock synchronization

Support for multi-master systems

Support for both 7-bit and 10-bit addressing

formats on the I

Build-in 8-bit timer for data transfers speed

adjusting

User-defined timing (data setup, start setup,

start hold, etc.)

Slave mode

Slave operation

Slave transmitter

Slave receiver

Supports 3 transmission speed modes

Standard (up to 100 kb/s)

High Speed (up to 3,4 Mb/s)

Allows operation from a wide range of input

clock frequencies

User-defined data setup time

Simple interface allows easy connection to

microprocessor/microcontroller devices

Interrupt generation

Fully synthesizable

Static synchronous design with positive

edge clocking and synchronous reset