IMPLEM ENTATIO N

BLOCK DIAGRAM

Figure below show the typical DI2CS imple-

mentations in system with Standard/Fast and

High-speed devices.

Figure below shows the DI2CS IP Core block

diagram.

address(1:0)

datai(7:0)

datao(7:0)

rd

cs

we

rst

clk

irq

CPU

Interface

sdai

sdao

scli

sclo

Input

Filter

Output

Register

Shift

Register

Clock

Stretching

Output

Register

Input

Filter

Control

Logic

Synchronization

Logic

Send

Data

Receive

Data

Receive

Data

Control

Register

Status

Register

Own

address

detection

open drain

open drain

sdai

SCL

SDA

sdao

sclo

scli

DI2CS

Master

device

scl

sda

CPU Interface

– Performs the interface func-

tions between DI2CS internal blocks and mi-

croprocessor. Allows easy connection of the

core to a microprocessor/microcontroller sys-

tem.

PERFORMANCE

Control Logic

– Manages execution of all

commands sent via interface. Synchronizes

internal data flow.

The following table gives a survey about the

Core area and performance in the ALTERA®

devices after Place & Route (all key features

have been included):

Shift Register

– Controls SDA line, performs

data and address shifts during the data

transmission and reception.

Device

Speed

grade

Logic Cells

MERCURY

-5

170

250 MHz

STRATIX

-5

170

260 MHz

CYCLONE

-6

170

220 MHz

APEX II

-7

170

270 MHz

APEX20KC

-7

170

150 MHz

APEX20KE

-1

170

120 MHz

APEX20K

-1

170

90 MHz

ACEX1K

-1

170

107 MHz

FLEX10KE

-1

170

107 MHz

MAX 7000AE

-5

83

96 MHz

MAX 3000A

-5

83

104 MHz

Control Register

– Contains five control bits

transmissions.

Status Register

– Contains seven status bits

DI2CS core.

Input Filter

– Performs spike filtering.

Synchronization Logic

– Performs DI2CS

core synchronization.

Core performance in ALTERA® devices

Clock Stretching

stretching when DI2CS core is not ready for

next transmission.

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