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Control Logic

– Manages execution of all

commands sent via interface. Synchronizes

internal data flow.

Shift Register

– Controls SDA line, performs

data and address shifts during the data

transmission and reception.

Input Filter

– Performs spike filtering.

Synchronization Logic

– Synchronizes data

and address shifts during the data transmis-

sion and reception. SCLI spikes are filtered

by this unit.

PERFORMANCE

The following table gives a survey about the

Core area and performance in the ALTERA®

devices after Place & Route (all key features

have been included):

Device

Speed

grade

Logic Cells

MERCURY

-5

95

220 MHz

STRATIX

-5

95

230 MHz

CYCLONE

-6

95

195 MHz

APEX II

-7

95

220 MHz

APEX20KC

-7

95

170 MHz

APEX20KE

-1

95

130 MHz

APEX20K

-1

95

94 MHz

ACEX1K

-1

95

99 MHz

FLEX10KE

-1

95

95 MHz

MAX 7000AE

-4

50

107 MHz

MAX 3000A

-4

50

107 MHz

MAX II

-3

75

154 MHz

Core performance in ALTERA® devices

below. It gives a briefly member characterization helping user to select the most suitable IP Core

for its application.

Design

DI2CM

2.1

-

-

DI2CS

2.1

-

-

-

-

DI2CSB

2.1

-

-

-

-

-

-

-

I