All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design

license allows using IP Core in

single FPGA bitstream and ASIC implementa-

tion. It also permits FPGA prototyping before

ASIC production.

Unlimited Designs

license allows using IP Core

in unlimited number of FPGA bitstreams and

ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time of use

limitations.

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Single Design license for

VHDL, Verilog source code called HDL Sour-

ce

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Unlimited Designs license for

HDL Source

Netlist

Upgrade from

Netlist to HDL Source

Single Design to Unlimited Designs

DESIGN FEATURES

PROGRAM MEMORY:

The DP80390 soft core is dedicated for

operation with Internal and External Pro-

gram Memory. It maximal linear size is

equal to 8 MB. Internal Program Memory

can be implemented as:

ROM located in address range between

0x0000

÷ (ROM

RAM located in address range between

External Program Memory can be im-

plemented as ROM or RAM located in ad-

INTERNAL DATA MEMORY:

The DP80390CPU can address Internal

Data Memory of up to 256 bytes The Inter-

nal Data Memory can be implemented as

Single-Port synchronous RAM.

EXTERNAL DATA MEMORY:

The DP80390CPU soft core can address

up to 16 MB of External Data Memory. Ex-

tra DPX (Data Pointer eXtended) register is

used for segments swapping.

USER

Up to 104 External (user) Special Func-

tion Registers (ESFRs) may be added to

the DP80390CPU design. ESFRs are

memory mapped into Direct Memory be-

tween addresses 0x80 and 0xFF in the

same manner as core SFRs and may oc-

cupy any address that is not occupied by a

core SFR.

WAIT STATES SUPPORT:

The DP80390CPU soft core is dedicated

for operation with wide range of Program

and Data memories. Slow Program and Ex-

ternal Data memory may assert a memory

Wait signal to hold up CPU activity.