Data Sheet

ADL8113

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 13 of 37

Figure 3. Pin Configuration

Table 11. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VDD1

Amplifier Drain Bias Voltage. See Figure 4 for the interface schematic.

2

RBIAS

Bias Setting Resistor. Connect a resistor between RBIAS and VDD1 to set IDQ. See Figure 5 for the

interface schematic.

3, 5, 8, 10 to 12, 14, 17, 19 to 22, 24 to 26, 28 GND

RF and DC Ground. See Figure 6 for the interface schematic.

4

RFIN

RF Input. The RFIN pin is DC-coupled and matched to 50Ω. A DC blocking capacitor is required if the

RF line potential is not equal to 0V DC. See Figure 7 for the interface schematic.

6, 7

VA , VB

Switch Control Inputs. See Figure 8 and Figure 9 for the interface schematics.

9, 13

OUT_B, IN_B

External Bypass Path B. The OUT_B and IN_B pins are DC-coupled and matched to 50Ω. A DC

blocking capacitor is required if the RF line potential is not equal to 0V DC. See Figure 7 for the

interface schematic.

15

VSS2

Switch Negative Bias Voltage.

16

VDD2

Switch Positive Bias Voltage.

18

RFOUT

RF Output. The RFOUT pin is DC-coupled and matched to 50Ω. A DC blocking capacitor is required if

the RF line potential is not equal to 0V DC. See Figure 7 for the interface schematic

23, 27

IN_A, OUT_A

External Bypass Path A. The IN_A and OUT_A pins are DC-coupled and matched to 50Ω. A DC

blocking capacitor is required if the RF line potential is not equal to 0V DC. See Figure 7 for the

interface schematic.

EPAD

Exposed Ground Pad. The exposed pad must be connected to RF and DC ground.