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ST10F273E 数据表(PDF) 102 Page - STMicroelectronics |
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ST10F273E 数据表(HTML) 102 Page - STMicroelectronics |
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102 / 179 page ![]() System reset ST10F273E 102/179 20.9 Reset summary A summary of the different reset events is reported in the table below. Table 50. Reset event Event RSTIN WDTCON Flags min max Power-on reset 0 0 N Asynch. 1 ms (VREG) 1.2 ms (Reson. + PLL) 10.2 ms (Crystal + PLL) - 1 1110 0 1 N Asynch. 1ms (VREG) - 1 1110 1 x x FORBIDDEN x x Y NOT APPLICABLE Hardware reset (asynchronous) 0 0 N Asynch. 500ns - 0 1110 0 1 N Asynch. 500ns - 0 1110 0 0 Y Asynch. 500ns - 0 1110 0 1 Y Asynch. 500ns - 0 1110 Short hardware reset (synchronous) (1) 1 0 N Synch. max (4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) 0 0110 1 1 N Synch. max (4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) 0 0110 10 Y Synch. max (4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) 0 0110 Activated by internal logic for 1024 TCL 11 Y Synch. max (4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) 0 0110 Activated by internal logic for 1024 TCL Long hardware reset (synchronous) 10 N Synch. 1032 + 12 TCL + max(4 TCL, 500ns) - 0 1110 11 N Synch. 1032 + 12 TCL + max(4 TCL, 500ns) - 0 1110 10 Y Synch. 1032 + 12 TCL + max(4 TCL, 500ns) - 0 1110 Activated by internal logic only for 1024 TCL 11 Y Synch. 1032 + 12 TCL + max(4 TCL, 500ns) - 0 1110 Activated by internal logic only for 1024 TCL |
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