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ST10F273E 数据表(PDF) 99 Page - STMicroelectronics |
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ST10F273E 数据表(HTML) 99 Page - STMicroelectronics |
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99 / 179 page ![]() ST10F273E System reset 99/179 Figure 29. System reset circuit Figure 30. Internal (simplified) reset circuitry RPD RSTIN VDD + C0 R0 External hardware VDD R2 + C1 R1 D2 D1 o.d. External reset source Open drain inverter VDD ST10F273 RSTOUT EINIT Instruction Trigger Clr clock Reset state machine Internal reset signal Reset Sequence (512 CPU clock cycles) SRST instruction watchdog overflow RSTIN VDD BDRSTEN VDD RPD Weak pull down (~200 µA) From/to exit power down circuit Asynchronous Reset Clr Q Set |
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