TMP86CM29BUG datasheet(69/196 Pages) TOSHIBA

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Page 55

TMP86CM29BUG

5.4 Port P5 (P57 to P50)

Port P5 is an 8-bit input/output port which is also used as a segment pins of LCD.

When used as input port, the respective output latch (P5DR) should be set to “1”.

During reset, the P5DR is initialized to “1”.

When used as a segment pins of LCD, the respective bit of P5LCR should be set to “1”. When used as an output

port, the respective P5LCR bit should be set to “0”.

P5 port output latch (P5DR) and P5 port terminal input (P5PRD) are located on their respective address.

When read the output latch data, the P5DR should be read and when read the terminal input data, the P5PRD reg-

ister should be read. If the terminal input data which is configured as LCD segment output is read, unstable data is

read.

Figure 5-5 Port P5

Port P5 control register

P5DR

(0005H)

R/W

543

P57

SEG16

P56

SEG17

P55

SEG18

P54

SEG19

P53

SEG20

P52

SEG21

P51

SEG22

P50

SEG23

(Initial value: 1111 1111)

P5LCR

(002AH)

543

(Initial value: 0000 0000)

P5LCR

Port P5/segment output control

(Set for each bit individually)

0: P5 input/output port

1: LCD segment output

R/W

P5PRD

(000BH)

Read only

543

P57

P56

P55

P54

P53

P52

P51

P50

Output latch

Data input (P5PRD)

Data input (P5DR)

Data output (P5DR)

LCD data output

STOP

OUTEN

P5LCRi

P5LCRi input

P5i

Note: i = 7

to 0

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