STR750FV0 datasheet(35/84 Pages) STMICROELECTRONICS

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STR750Fxx STR751Fxx STR752Fxx STR755Fxx

Electrical parameters

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5.3.2

Operating conditions at power-up / power-down

Subject to general operating conditions for TA.

5.3.3

Embedded voltage regulators

Subject to general operating conditions for VDD_IO, and TA

Table 11.

Operating conditions at power-up / power-down

Symbol

Parameter

Conditions

Min(1)

Data guaranteed by characterization, not tested in production.

Typ

Max(1)

Unit

tVDD_IO

VDD_IO rise time rate

µs/V

ms/V

tV18

V18 rise time rate

(1)

When 1.8 V power is supplied

externally

µs/V

ms/V

Table 12.

Embedded voltage regulators

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VMVREG

MVREG power supply(1)

VMVREG is observed on the V18, V18REG and V18BKP pins except in the following case:

- In STOP mode with MVREG OFF (LP_PARAM13 bit). See note 2.

- In STANDBY mode. See note 2.

load <150 mA

1.65

1.80

1.95

VLPVREG

LPVREG power supply(2)

In STANDBY mode, VLPVREG is observed on the V18BKP pin

In STOP mode, VLPVREG is observed on the V18, V18REG and V18BKP pins.

load <10 mA

1.30

1.40

1.50

tVREG_PWRUP

(1)

Voltage Regulators start-up

time (to reach 90% of final V18

value) at VDD_IO power-up

(3)

Once VDD_IO has reached 3.0 V, the RSM (Regulator Startup Monitor) generates an internal RESET

during this start-up time.

VDD_IO rise

slope = 20 µs/V

µs

VDD_IO rise

slope = 20 ms/V

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