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PCM1774RGPR 数据表(PDF) 16 Page - Texas Instruments |
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PCM1774RGPR 数据表(HTML) 16 Page - Texas Instruments |
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16 / 49 page ![]() www.ti.com Audio Data Formats and Timing DIN BCK LRCK 50%ofV IO tw(BCH) tw(BCL) t(LB) 50%ofV IO 50%ofV IO tw(BCY) t(BL) t(DS) t(DH) PCM1774 SLAS551 – JULY 2007 The PCM1774 supports I2S, right-justified, left-justified, and DSP formats. The data formats are shown in Figure 16 and are selected using registers 70 and 81 (RFM[1:0], PFM[1:0]). All formats require binary 2s-complement, MSB-first audio data. The default format is I2S. Figure 14 shows a detailed timing diagram. PARAMETERS MIN MAX UNITS BCK pulse cycle time (I2S, left- and right-justified formats) 1/(64 fS) (1) t(BCY) BCK pulse cycle time (DSP format) 1/(256 fS) (1) tw(BCH) BCK high-level time 35 ns tw(BCL) BCK low-level time 35 ns t(BL) BCK rising edge to LRCK edge 10 ns t(LB) LRCK edge to BCK rising edge 10 ns t(DS) DIN set up time 10 ns t(DH) DIN hold time 10 ns tr Rising time of all signals 10 ns tf Falling time of all signals 10 ns (1) fS is the sampling frequency. Figure 14. Audio Interface Timing (Slave Mode) 16 Submit Documentation Feedback |
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