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PCM1774RGPRG4 数据表(PDF) 17 Page - Texas Instruments |
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PCM1774RGPRG4 数据表(HTML) 17 Page - Texas Instruments |
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17 / 49 page ![]() www.ti.com DIN BCK (Output) LRCK (Output) 50%ofV IO SCKI t(SCY) t(DL) 50%ofV IO 50%ofV IO 50%ofV IO tw(BCH) tw(BCL) t(DB) t(DB) t(BCY) t(DH) t(DS) PCM1774 SLAS551 – JULY 2007 PARAMETERS MIN MAX UNIT t(SCY) SCKI pulse cycle time 1/(256 fS) (1) t(DL) LRCK edge from SCKI rising edge 0 40 ns t(DB) BCK edge from SCKI rising edge 0 40 ns t(BCY) BCK pulse cycle time 1/(64 fS) (1) tw(BCH) BCK high level time 146 ns tw(BCL) BCK low level time 146 ns t(DS) DATA setup time 10 ns t(DH) DATA hold time 10 ns (1) fS is up to 48 kHz. fS is the sampling frequency. Figure 15. Audio Interface Timing (Master Mode) 17 Submit Documentation Feedback |
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