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PCM1774RGPRG4 数据表(PDF) 22 Page - Texas Instruments

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部件名 PCM1774RGPRG4
功能描述  16-Bit, Low-Power Stereo Audio DAC With Analog Mixing, Line and Headphone Outputs
PDF  49 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

PCM1774RGPRG4 数据表(HTML) 22 Page - Texas Instruments

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R0002-02
M: Master Device S: Slave Device St: Start Condition
Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge
W: Write R: Read
Transmitter
M
M
M
S
Data Type
St
Slave Address
W
ACK
M
Reg Address
M
Sr
M
Slave Address
S
ACK
M
R
S
ACK
M
Sp
M
NACK
S
Read Data
Timing Diagram
PCM1774
SLAS551 – JULY 2007
NOTE: The slave address after the repeated start condition must be the same as the previous slave address.
Figure 22. Read Operation
PARAMETERS
CONDITIONS
MIN
MAX
UNIT
fSCL
SCL clock frequency
Standard
100
kHz
t(BUF)
Bus free time between a STOP and START condition
Standard
4.7
μs
t(LOW)
Low period of the SCL clock
Standard
4.7
μs
t(HI)
High period of the SCL clock
Standard
4
μs
t(RS-SU)
Setup time for START condition
Standard
4.7
μs
t(S-HD)
Hold time for START condition
Standard
4
μs
t(D-SU)
Data setup time
Standard
250
ns
t(D-HD)
Data hold time
Standard
0
900
ns
t(SCL-R)
Rise time of SCL signal
Standard
20 + 0.1 CB
1000
ns
t(SCL-R1)
Rise time of SCL signal after a repeated START condition and
Standard
20 + 0.1 CB
1000
ns
after an acknowledge bit
t(SCL-F)
Fall time of SCL signal
Standard
20 + 0.1 CB
1000
ns
t(SDA-R)
Rise time of SDA signal
Standard
20 + 0.1 CB
1000
ns
t(SDA-F)
Fall time of SDA signal
Standard
20 + 0.1 CB
1000
ns
t(P-SU)
Setup time for STOP condition
Standard
4
μs
CB
Capacitive load for SDA and SCL line
400
pF
t(SP)
Pulse duration of suppressed spike
25
ns
Figure 23. I2C Interface Timing
22
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