JBT6L77-AS

2001-12-18

8

Pin Function

Pin Name

I/O

Function

DI/O

DO/I

I/O

Data transfer enable pin

These pins are used to input/output grayscale data.

Input and output are switched as shown below according to the setting of the U/D pin.

U/D

DI/O

DO/I

H

Input

Output

L

Output

Input

When set for input

A high on DI/O or DO/I is latched into the internal logic synchronously with the rising edge of

CPH. When the internal circuit is in standby state, the device is ready to transfer data.

The grayscale data is latched in sequentially, starting at the next rise of CPH.

When set for output

The pin is used to transfer the enable signal to the JBT6L77-AS at the next stage of the LCD

driver.

The pin enters standby state after outputting a high.

U/D

I

Transfer direction select pin

This pin controls the direction in which the data is transferred into the sampling register.

Data is transferred synchronously with each rising edge of CPH in one of the following

sequences:

When U/D is high, data is transferred in the order SA1 to SC1, SA2 to SC2, SA3 to SC3, …

When U/D is low, the direction is reversed to give SA80 to SC80, SA79 to SC79,

SA78 to SC78, …

The voltage applied to this pin must be a DC-level voltage that is either high or low.

CPH

I

Sampling clock input

This clock input is used to transfer grayscale data.

In sync with the rising edge of CPH, writes grayscale data bus data to the sampling register.

DA0 to DA5

DB0 to DB5

DC0 to DC5

I

Grayscale data bus

The data inputs consist of 6-bit word for each three channel that are transferred in parallel at the

rising edge of CPH. The relationship between the grayscale data and the weight of each bit is

as follows:

Grayscale data

= 32 ´ Dw5 + 16 ´ Dw4 + 8 ´ Dw3 + 4 ´ Dw2 + 2 ´ Dw1 + Dw0

(*) w

= A, B, C

LOAD

I

Data load input pin

When a high voltage supplys to the load input, the data is transferred from the Sampling register

to the Load register synchronously at the rising edge of CPH.

(Note) After High level is input to this pin (LOAD), input CPH for at least three cycles in the

same cycle as that for sampling.

· When LOAD = Low level, output is at high impedance.

· When LOAD = High level, output corresponds to grayscale data.

V0 to V10

I

Reference analog input pins

These pins are used to input the voltage used for the DAC.

TESTB

I

Test pin

SA1 to SA80

SB1 to SB80

SC1 to SC80

O

LCD panel drive pins

Analog power supply pin

Digital power supply pin.

GND pin