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JBT6L77-AS 数据表(PDF) 3 Page - Toshiba Semiconductor |
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JBT6L77-AS 数据表(HTML) 3 Page - Toshiba Semiconductor |
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3 / 20 page ![]() JBT6L77-AS 2001-12-18 3 PAD Layout Chip size: 1.56 ´ 13.28 (mm) : Cross point Output pad 240, 50 mm pitch, two-step zigzag allocation SB80 SC80 SA80 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY 11 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY 11 SB1 SC1 SA1 DUMMY Chip center (0,0) 6 6 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 6 6 3 2222 2 AVDD VSS DVDD V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 CPH U/D TEG DC5 DC4 DC3 DC2 DC1 LOAD DO/I TESTB DC0 V0 DB5 DB4 DB3 DB1 DB0 DA5 DA4 DA3 DA2 DA1 DI/O DA0 VSS AVDD DB2 3 3 TEG TEG Alignment mark Alignment mark 【Unit: mm】 ◆ Output side dummy ◆ Output pins (SA1 to SC80) 45 40 60 40 60 40 60 40 20 20 90 50 40 90 45 ◆ Input pins (V0 to V10, LOAD, TESTB) 40 45 45 20 40 20 20 50 40 20 40 90 ◆ Input pins (DVDD) 70 20 70 45 45 35 35 20 70 90 ◆ Input pins (others) 45 50 45 20 20 50 50 90 25 25 ◆ Input pins (AVDD, VSS) 75 37.5 37.5 20 75 20 75 45 90 45 100 50 50 50 ◆ Short-side dummy pins ◆ Alignment mark 90 90 30 30 30 30 30 30 Pattern prohibited 50 50 50 50 X ( +) Y ( +) |
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