AD8372ACPZ-R71 datasheet(5/16 Pages) AD

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AD8372

Rev. 0 | Page 5 of 16

SERIAL CONTROL INTERFACE TIMING

DON'T CARE

WRITE BIT

LSB

LSB + 1

LSB + 2

MSB – 2

MSB – 1

MSB

tDH

tDS

tLH

tLS

tPW

tCLK

NOTES

1. THE FIRST SDI BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL GAIN WORD REGISTER. FOR A

WRITE OPERATION, THE FIRST BIT SHOULD BE A HIGH LOGIC LEVEL, FOR A READ OPERATION THE FIRST BIT SHOULD BE A LOGIC 1.

THE GAIN WORD BIT IS THEN REGISTERED INTO THE SDI PIN ON THE NEXT RISING CLOCK.

CLK1 OR CLK2

LCH1 OR LCH2

SDI1 OR SDI2

Figure 2. Write Mode Timing Diagram

tLH

tDH

tDS

tLS

tPW

tCLK

READ BIT

LSB

LSB + 1

LSB + 2

MSB – 2

MSB – 1

MSB

NOTES

1. THE GAIN WORD BIT IS UPDATED AT THE SDO PIN ON THE FALLING CLOCK EDGE.

CLK1 OR CLK2

LCH1 OR LCH2

SDI1 OR SDI2

SDO1 OR SDO2

Figure 3. Read Mode Timing Diagram

Table 3. Serial Programming Timing Parameters

Parameter

Min

Unit

Clock Pulse Width (tPW)

Clock Period (tCK)

Write Mode

Setup Time Data vs. Clock (tDS)

0.0

Hold Time Data vs. Clock (tDH)

1.6

Setup Time Latch vs. Clock (tLS)

−1.8

Hold Time Latch vs. Clock (tLH)

2.0

Read Mode

Clock to Data Out (tD)

4.5

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