ST72F521 datasheet(136/215 Pages) STMICROELECTRONICS

136 / 215 page

ST72F521, ST72521B

136/215

CONTROLLER AREA NETWORK (Cont’d)

10.8.4 Register Description

The CAN registers are organized as 6 general pur-

pose registers plus 5 pages of 16 registers span-

ning the same address space and primarily used

for message and filter storage. The page actually

selected is defined by the content of the Page Se-

lection Register.

10.8.4.1 General Purpose Registers

INTERRUPT STATUS REGISTER (ISR)

Read/Write

Reset Value: 00h

Bit 7 = RXIF3 Receive Interrupt Flag for Buffer 3

− Read/Clear

Set by hardware to signal that a new error-free mes-

sage is available in buffer 3.

Cleared by software to release buffer 3.

Also cleared by resetting bit RDY of BCSR3.

Bit 6 = RXIF2 Receive Interrupt Flag for Buffer 2

− Read/Clear

Set by hardware to signal that a new error-free

message is available in buffer 2.

Cleared by software to release buffer 2.

Also cleared by resetting bit RDY of BCSR2.

Bit 5 = RXIF1 Receive Interrupt Flag for Buffer 1

− Read/Clear

Set by hardware to signal that a new error-free mes-

sage is available in buffer 1.

Cleared by software to release buffer 1.

Also cleared by resetting bit RDY of BCSR1.

Bit 4 = TXIF Transmit Interrupt Flag

− Read/Clear

Set by hardware to signal that the highest priority

message queued for transmission has been suc-

cessfully transmitted.

Cleared by software.

Bit 3 = SCIF Status Change Interrupt Flag

− Read/Clear

Set by hardware to signal the reception of a domi-

nant bit while in standby mode. In Run mode this bit

is set when EPVS is set or reset (refer to Figure 71.

CAN Error State Diagram). This bit also signals any

receive error when ESCI=1.

Cleared by software.

Bit 2 = ORIF Overrun Interrupt Flag

− Read/Clear

Set by hardware to signal that a message could not

be stored because no receive buffer was available.

Cleared by software.

Bit 1 = TEIF Transmit Error Interrupt Flag

− Read/Clear

Set by hardware to signal that an error occurred dur-

ing the transmission of the highest priority message

queued for transmission.

Cleared by software.

Bit 0 = EPND Error Interrupt Pending

− Read Only

Set by hardware when at least one of the three error

interrupt flags SCIF, ORIF or TEIF is set.

Reset by hardware when all error interrupt flags

have been cleared.

Caution:

Interrupt flags are reset by writing a “0” to the cor-

responding bit position. The appropriate way con-

sists in writing an immediate mask or the one’s com-

plement of the register content initially read by the

interrupt handler. Bit manipulation instruction

BRES should never be used due to its read-modify-

write nature.

RXIF3 RXIF2 RXIF1

TXIF

SCIF

ORIF

TEIF

EPND

ST72F521 数据表(PDF) 136 Page - STMicroelectronics

ST72F521 数据表(HTML) 136 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ST72F521 数据表(PDF) 136 Page - STMicroelectronics

ST72F521 数据表(HTML) 136 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载