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ST72F521 数据表(PDF) 140 Page - STMicroelectronics |
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ST72F521 数据表(HTML) 140 Page - STMicroelectronics |
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140 / 215 page  ST72F521, ST72521B 140/215 CONTROLLER AREA NETWORK (Cont’d) 10.8.4.2 Paged Registers LAST IDENTIFIER HIGH REGISTER (LIDHR) Read/Write Reset Value: Undefined LID[10:3] are the most significant 8 bits of the last Identifier read on the CAN bus. LAST IDENTIFIER LOW REGISTER (LIDLR) Read/Write Reset Value: Undefined LID[2:0] are the least significant 3 bits of the last Identifier read on the CAN bus. LRTR is the last Remote Transmission Request bit read on the CAN bus. LDLC[3:0] is the last Data Length Code read on the CAN bus. TRANSMIT ERROR COUNTER REG. (TECR) Read Only Reset Value: 00h TEC[7:0] is the least significant byte of the 9-bit Transmit Error Counter implementing part of the fault confinement mechanism of the CAN protocol. In case of an error during transmission, this counter is incremented by 8. It is decremented by 1 after every successful transmission. When the counter value exceeds 127, the CAN controller enters the error passive state. When a value of 256 is reached, the CAN controller is disconnected from the bus. RECEIVE ERROR COUNTER REG. (RECR) Page: 00h — Read Only Reset Value: 00h REC[7:0] is the Receive Error Counter implement- ing part of the fault confinement mechanism of the CAN protocol. In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN stand- ard. After every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. When the counter value exceeds 127, the CAN controller enters the error passive state. IDENTIFIER HIGH REGISTERS (IDHRx) Read/Write Reset Value: Undefined ID[10:3] are the most significant 8 bits of the 11-bit message identifier.The identifier acts as the mes- sage’s name, used for bus access arbitration and acceptance filtering. 70 LID10 LID9 LID8 LID7 LID6 LID5 LID4 LID3 70 LID2 LID1 LID0 LRTR LDLC 3 LDLC 2 LDLC 1 LDLC 0 70 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 70 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 70 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 |
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