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Cortex-M33 Components

Processor Core

The processor core provides:

Limited dual-issue of common 16-bit instruction pairs

Single cycle 32×32-bit multiplier

Integer divide unit with support for operand-dependent early termination

Support for interrupted continuable load and store multiple operations

Load and store operations that both support precise bus errors

To support Arm Custom Instruction, the processor core includes an optional

CDE module. This module is used to execute user-defined instructions that work

on general-purpose registers

Security Attribution and Memory Protection

The Cortex-M33 processor supports the Armv8-M Protected Memory System Architecture

(PMSA) that provides programmable support for memory protection using a number of

software controllable regions.

Memory regions can be programmed to generate faults when accessed inappropriately

by unprivileged software reducing the scope of incorrectly written application code.

The architecture includes fault status registers to allow an exception handler to determine

the source of the fault and to apply corrective action or notify the system.

The Cortex-M33 processor also includes optional support for defining memory regions as

Secure or Non- secure, as defined in the Armv8-M security extension, and protecting the

regions from accesses with an inappropriate level of security.

Floating-point Unit

The FPU provides:

Instructions for single-precision (C programming language float type)

data-processing operations

Instructions for double-precision (C double type) load and store operations

Combined multiply-add instructions for increased precision (Fused MAC)

Hardware support for conversion, addition, subtraction, multiplication with optional

accumulate, division, and square-root

Hardware support for denormals and all IEEE Standard 754-2008 rounding modes

32 32-bit single-precision registers or 16 64-bit double-precision registers

Lazy floating-point context save. Automated stacking of floating-point state is delayed

until the ISR attempts to execute a floating-point instruction. This reduces the latency

to enter the ISR and removes floating-point context save for ISRs that do not

use floating-point