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To support Arm Custom Instructions, the FPU includes an optional floating-point

CDE module. This module is used to execute user-defined instructions that work

on floating-point registers. If the optional FPU is not present, then the optional

floating-point CDE module is not present either

Nested Vectored Interrupt Controller

The Nested Vectored Interrupt Controller (NVIC) is closely integrated with the core

to achieve low-latency interrupt processing.

Functions of the NVIC include:

External interrupts, configurable from 1 to 480 using a contiguous or non-contiguous

mapping. This is configured at implementation

Configurable levels of interrupt priority from 8 to 256. This is configured

at implementation. Dynamic reprioritization of interrupts

Priority grouping. This enables selection of preempting interrupt levels

and non-preempting interrupt levels

Support for tail-chaining and late arrival of interrupts. This enables back-to-backinterrupt

processing without the overhead of state saving and restoration between interrupts

Optional support for the Armv8-M security extension. Secure interrupts can be

prioritized above any Non-secure interrupt

Coprocessor Interface

The Cortex-M33 processor supports an external coprocessor interface which

allows the integration of tightly coupled accelerator hardware with the processor.

The programmers model allows software to communicate with the hardware using

architectural coprocessor instructions.

The external coprocessor interface:

Supports up to eight separate coprocessors, CP0-CP7, depending on your

implementation. The remaining coprocessor numbers, C8-C15, are reserved. CP10

and CP11 are always reserved for hardware floating-point. For more information,

see the Armv8-M Architecture Reference Manual

Supports low-latency data transfer from the processor to and from

the accelerator components

Has a sustained bandwidth up to twice of the processor memory interface

Cross Trigger Interface Unit

The optional CTI enables the debug logic, micro trace buffer (MTB), and ETM to interact

with each other and with other CoreSight components.