Data Sheet

ADPL42002

analog.com

Rev. 1

8 of 22

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. 6-Lead LFCSP Pin Configuration

Figure 4. 8-Lead SOIC Pin Configuration

Pin Descriptions

Table 5. Pin Descriptions

PIN

NAME

DESCRIPTION

6-Lead

LFCSP

8-Lead

SOIC

1

1, 2

VOUT

Regulated Output Voltage. Bypass VOUT to GND with a 2.2µF or greater

capacitor.

2

3

SENSE/ADJ

Sense Input (SENSE). Connect to load. An external resistor divider may also

set the output voltage higher than the fixed output voltage (ADJ).

3

4

GND

Ground.

4

5

EN

The Enable Pin Controls the operation of the LDO. Drive EN high to turn on

the regulator. Drive EN low to turn off the regulator. For automatic startup,

connect EN to VIN.

5

6

SS

Soft Start. An external capacitor connected to this pin determines the soft-

start time. Leave this pin open for a typical 380μs start-up time. Do not

ground this pin. 400µs is a typical soft-start time in the rest of DS.

6

7, 8

VIN

Regulator Input Supply. Bypass VIN to GND with a 2.2µF or greater capacitor.

EP

Exposed Pad. The exposed pad on the bottom of the package enhances

thermal performance and is electrically connected to GND inside the

package. It is recommended that the exposed pad connect to the ground

plane on the board.

3

GND

1

VOUT

2

SENSE/ADJ

4 EN

6 VIN

5 SS

ADPL42002

TOP VIEW

(Not to Scale)

EXPOSED PAD

NOTES

1. EXPOSED PAD. THE EXPOSED PAD ON THE BOTTOM OF

THE PACKAGE ENHANCES THERMAL PERFORMANCE

AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE

PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED

PAD CONNECT TO THE GROUND PLANE ON THE BOARD.

TOP VIEW

(Not to Scale)

VOUT 1

VOUT 2

SENSE/ADJ 3

GND 4

VIN

8

VIN

7

SS

6

EN

5

NOTES

1. EXPOSED PAD. THE EXPOSED PAD ON THE BOTTOM OF

THE PACKAGE ENHANCES THERMAL PERFORMANCE

AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE

PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED

PAD CONNECT TO THE GROUND PLANE ON THE BOARD.

ADPL42002

EXPOSED PAD