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Rev C, 4/27/2023

Page 34

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FlexSense® I-Series Programmable

Incremental Encoder

FS210/FS310 Datasheet

The FS210/FS310 acknowledges (A) each byte successfully matched slave address and after every byte during a slave write

sequence. If the slave address embedded in the SA-W byte does not match the slave address assigned to the FS210/FS310,

then the device negative-acknowledges (A\) the SA-W byte and all subsequent bytes until the next detected start (S)

condition.

For a Write Memory command sequence, the I2C bus master should follow the slave address immediately (with no

intervening stop, start, or start-repeat condition) by a 2-byte register address (LSB first) and then a series of data bytes,

each of which is acknowledged (A) by the FS210/FS310. The first such data byte is stored in the device register specified by

the 2-byte target address in the preamble. Subsequent data bytes, if any, are stored at consecutively increasing register

addresses. After the last data byte is transmitted, the I2C bus master should transmit a stop condition (P) to terminate the

Slave Write sequence. This sequence is depicted graphically in the figure below, where elements in black indicate

transmission from the I2C bus master to the device and elements in blue indicate transmission from the device to the I2C

bus master.

S

A

A

Reg Addr

LS Byte

A

SA-W

Reg Addr

MS Byte

Data

A

...

Data

A P

Figure 12: Write Memory Command Sequence

For a Read Memory command sequence, the I2C bus master should issue a slave write followed by the 2-byte register

address, a Stop (S) condition, then a “Slave Address – Read” (SA-R) byte (assigned 7-bit I2C slave address a “Read” direction

bit appended at the least-significant end, or ‘h63), which the FS210/FS310 acknowledges (A), provided the 7-bit slave

address embedded in the SA-R byte matches that assigned to the device (0110001b) and which it negative-acknowledges

(A\) otherwise. Following the SA-R byte, the device transmits a series of data bytes, of which the first is the contents of the

register at the target address specified in the 3-byte preamble and of which subsequent bytes, if any, are the contents of

registers at consecutively increasing addresses. The I2C bus master should acknowledge (A) a data byte if it is not the last

data byte intended to be read, and it should negative-acknowledge (A\) the last data byte it intends to read. After such a

negative-acknowledgement from the I2C bus master, the device ignores all I2C traffic until the next start or start-repeat

condition is issued.

CAUTION: The I2C Repeated Start (Sr) command is not implemented on the FS210/FS310. Any usage of the Repeated Start

will give undefined behavior.

S

A

A

Reg Addr

LS Byte

A

SA-W

Reg Addr

MS Byte

Data

A

...

Data

A\ P

P S

SA-R

A

Figure 13: Read Memory Command Sequence