DS92001

SNLS147F – JUNE 2002 – REVISED APRIL 2013

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AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LVDS OUTPUT AC SPECIFICATIONS (OUT)

tPHLD

Differential Propagation Delay High

VID = 200mV, VCM = 1.2V,

1.0

1.4

2.0

ns

to Low(2)

RL = 27Ω or 50Ω, CL = 15pF

See Figure 5 and Figure 6

tPLHD

Differential Propagation Delay Low

1.0

1.4

2.0

ns

to High(2)

tSKD1

Pulse Skew |tPLHD − tPHLD|

0

20

200

ps

(measure of duty cycle)(3)(4)

tSKD3

Part-to-Part Skew(3)(5)

0

200

300

ps

tSKD4

Part-to-Part Skew(3)(6)

0

1

ns

tLHT

Rise Time(3)(2)

RL = 50Ω or 27Ω, CL = 15pF

0.350

0.6

1.0

ns

20% to 80% points

See Figure 5 and Figure 7

tHLT

Fall Time(3)(2)

0.350

0.6

1.0

ns

80% to 20% points

tPHZ

Disable Time (Active High to Z)

RL = 50Ω, CL = 15pF See Figure 8 and Figure 9

3

25

ns

tPLZ

Disable Time (Active Low to Z)

3

25

ns

tPZH

Enable Time (Z to Active High)

100

120

ns

tPZL

Enable Time (Z to Active Low)

100

120

ns

tDJ

LVDS Data Jitter, Deterministic

VID = 300mV; PRBS = 2

23 − 1 data; V

CM = 1.2V at

78

ps

(Peak-to-Peak)(7)

400Mbps (NRZ)

tRJ

LVDS Clock Jitter, Random(7)

VID = 300mV; VCM = 1.2V at 200MHz clock

36

ps

fMAX

Maximum specified frequency(8)

VID = 200mV, VCM = 1.2V

200

300

MHz

(1)

All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.

(2)

Propagation delay, rise and fall times are specified by design and characterization to 200MHz. Generator for these tests: 50MHz

≤ f ≤

200MHz, Zo = 50

Ω, tr, tf ≤ 0.5ns. Generator used was HP8130A (300MHz capability).

(3)

The parameters are specified by design. The limits are based on statistical analysis of the device performance over the PVT (process,

voltage and temperature) range.

(4)

tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative

going edge of the same channel (a measure of duty cycle).

(5)

tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This

specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. This parameter

specified by design and characterization.

(6)

tSKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices

over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|

differential propagation delay.

(7)

The parameters are specified by design. The limits are based on statistical analysis of the device performance over the PVT range with

the following test equipment setup: Agilent 86130A used as stimulus, 5 feet of RG142B cable with DUT test board and Agilent 86100A

(digital scope mainframe) with Agilent 86122A (20GHz scope module). Data input jitter pk to pk = 22 picoseconds; Clock input jitter = 24

picoseconds; tDJ measured 100 picoseconds, tRJ measured 60 picoseconds.

(8)

fMAX test: Generator (HP8133A or equivalent), Input duty cycle = 50%. Output criteria: VOD ≥ 200mV, Duty Cycle better than 45/55%.

This specification is specified by design and characterization. A minimum is specified, which means that the device will operate to

specified conditions from DC to the minimum specified AC frequency. The typical value is always greater than the minimum

specification.

4

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