CC1050-RTR1 datasheet(15/43 Pages) TI2

15 / 43 page

CC1050

SWRS044

Page 15 of 40

Signal interface

The signal interface consists of DI and

DCLK and is used for the data to be

transmitted. DI is the data input line and

DCLK provides a synchronous clock

during data transmission.

The

CC1050 can be used with NRZ (Non-

Return-to-Zero) data or Manchester (also

known as bi-phase-level) encoded data.

CC1050 can be configured for three

different data formats:

Synchronous NRZ mode.

CC1050 provides

the data clock at DCLK, and DI is used as

data input. Data is clocked into

CC1050 at

the rising edge of DCLK. The data is

modulated at RF without encoding.

CC1050

can be configured for the data rates 0.6,

1.2, 2.4, 4.8, 9.6, 19.2, 38.4 or 76.8 kbit/s.

See Figure 7.

Synchronous Manchester encoded mode.

CC1050 provides the data clock at DCLK,

and DI is used as data input. Data is

clocked into

CC1050 at the rising edge of

DCLK and should be in NRZ format. The

data is modulated at RF with Manchester

code. The encoding is done by

CC1050. In

this mode

CC1050 can be configured for

the data rates 0.3, 0.6, 1.2, 2.4, 4.8, 9.6,

19.2 or 38.4 kbit/s. The 38.4 kbit/s rate

corresponds to the maximum 76.8 kBaud

due to the Manchester encoding. See

Figure 8.

Transparent Asynchronous UART mode.

In transmit mode DI is used as data input.

The data is modulated at RF without

synchronisation or encoding. Data rates in

the range from 0.6 to 76.8 kBaud can be

used. See Figure 9.

Manchester encoding

In the Synchronous Manchester encoded

mode

CC1050 uses Manchester coding

when

modulating

the

data.

The

Manchester code is based on transitions;

a “0” is encoded as a low-to-high

transition, a “1” is encoded as a high-to-

low transition. See Figure 10.

The Manchester code ensures that the

signal has a constant DC component,

which

necessary

some

FSK

demodulators. Using this mode also

ensures compatibility with CC400/CC900

designs.

DCLK

“RF”

Clock provided by CC1050

FSK modulating signal (NRZ),

internal in CC1050

Data provided by microcontroller

DCLK

“RF”

Clock provided by CC1050

FSK modulating signal (NRZ),

internal in CC1050

Data provided by microcontroller

Figure 7. Synchronous NRZ mode

Not Recommended for New Designs

CC1050-RTR1 数据表(PDF) 15 Page - Texas Instruments

CC1050-RTR1 数据表(HTML) 15 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

数据表下载