CC1050-RTR1 datasheet(12/43 Pages) TI2

12 / 43 page

CC1050

SWRS044

Page 12 of 40

3-wire Serial Configuration Interface

CC1050 is configured via a simple 3-wire

interface (PDATA, PCLK and PALE).

There are 19 8-bit configuration registers,

each addressed by a 7-bit address. A

Read/Write bit initiates a read or write

operation. A full configuration of

CC1050

requires sending 19 data frames of 16 bits

each (7 address bits, R/W bit and 8 data

bits).

The

time

needed

for

full

configuration

depend

the

PCLK

frequency. With a PCLK frequency of 10

MHz the full configuration is done in less

than 30

µs. Setting the device in power

down mode requires sending one frame

only and will in this case take less than 2

µs. All registers are also readable.

In each write-cycle 16 bits are sent on the

PDATA-line. The seven most significant

bits of each data frame (A6:0) are the

address-bits. A6 is the MSB (Most

Significant Bit) of the address and is sent

as the first bit. The next bit is the R/W bit

(high for write, low for read). During

address and R/W bit transfer the PALE

(Program Address Latch Enable) must be

kept low. The 8 data-bits are then

transferred (D7:0). See Figure 4.

The timing for the programming is also

shown in Figure 4 with reference to Table

2. The clocking of the data on PDATA is

done on the negative edge of PCLK.

When the last bit, D0, of the 8 data-bits

has been loaded, the data word is loaded

in the internal configuration register.

The configuration data is stored in internal

RAM and is valid after power-down mode,

but not when the power-supply is turned

off. The registers can be programmed in

any order.

The configuration registers can also be

read by the microcontroller via the same

configuration interface. The seven address

bits are sent first, then the R/W bit set low

to initiate the data read-back.

CC1050 then

returns the data from the addressed

output and must be tri-stated (or set high n

the case of an open collector pin) by the

microcontroller during the data read-back

(D7:0). The read operation is illustrated in

Figure 5.

Figure 4. Configuration registers write operation

PCLK

PDATA

PALE

Address

Write mode

Data byte

CH,min

CL,min

Not Recommended for New Designs

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