7 Application and Implementation

7.1 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the

Recommended Operating Conditions table.

Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single

supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each

power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and

a 1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as

possible for best results.

7.2 Layout Guidelines

7.2.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions

of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only

three of the four buffer gates are used. Such input pins should not be left unconnected because the undefined

voltages at the outside connections result in undefined operational states. Specified below are the rules that

must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high

or low bias to prevent them from floating. The logic level that should be applied to any particular unused input

depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense

or is more convenient. Floating outputs is generally acceptable, unless the part is a transceiver. If the transceiver

has an output enable pin it will disable the outputs section of the part when asserted. This will not disable the

input section of the I.O’s so they also cannot float when disabled.

CD54AC373, CD74AC373, CD54ACT373, CD74ACT373

SCHS289A – DECEMBER 1998 – REVISED MAY 2024

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