PCF8563

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Product data sheet

Rev. 11 — 26 October 2015

31 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

[1]

CL is a calculation of Ctrim and COSCO in series:

.

[2]

Unspecified for fCLKOUT = 32.768 kHz.

[3]

All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage

swing of VSS to VDD.

[4]

A detailed description of the I2C-bus specification is given in Ref. 11 “UM10204”.

[5]

I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

tf

fall time of both SDA and SCL signals

-

-

0.3

s

tBUF

bus free time between a STOP and START

condition

1.3

-

-

s

Cb

capacitive load for each bus line

-

-

400

pF

tSU;DAT

data set-up time

100

-

-

ns

tHD;DAT

data hold time

0

-

-

ns

tSU;STO

set-up time for STOP condition

0.6

-

-

s

tw(spike)

spike pulse width

on bus

-

-

50

ns

Table 30.

Dynamic characteristics …continued

VDD = 1.8 V to 5.5 V; VSS =0V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs =40 k; CL = 8 pF; unless otherwise

specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

C

L

C

trim

C

OSCO





C

trim

C

OSCO

+



-----------------------------------------

=

Fig 27. I2C-bus timing waveforms

SDA

mga728

SDA

SCL

tSU;STA

tSU;STO

tHD;STA

tBUF

tLOW

tHD;DAT

tHIGH

tr

tf

tSU;DAT