LM98640CVAL datasheet(28/55 Pages) TI2

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PGA GAIN vs. PGA CODE

PGA REGISTER VALUE

-1

-2

-3

-4

224

192

160

128

Overall Gain (dB)

Overall Gain (V/V)

Gain (dB) =

20Log10(180/(277-PGA Code))

Gain (V/V) =

(180/(277-PGA Code))

LM98640QML-SP

SNAS461G – MAY 2010 – REVISED NOVEMBER 2018

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Product Folder Links: LM98640QML-SP

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Feature Description (continued)

7.3.2.3 VCLP DAC

The VCLP pin can be used to provide the reference level for incoming signals in Sample and Hold Mode. The pin

is driven by the VCLP DAC, the VCLP DAC has five bits and has an approximate range of 2.9 V. The VCLP DAC

is controlled by the VCLP Control Register (0×04), and programmable through the serial interface.

7.3.3 Programmable Gain

The LM98640QML-SP provides two independent gain stages. The first stage is in the input CDS/SH circuit. The

second is in the form of a Programmable Gain Amplifier (PGA).

7.3.3.1 CDS/SH Stage Gain

The CDS/SH gain is programmable to either 0-dB or 6-dB gain. The load presented to the user in 6-dB mode is

roughly twice the switched load of 0-dB mode. The CDS/SH gain settings affect both channels. The CDS/SH

gain bit is located in bit 2 of the Main Configuration register, and programmable through the serial interface.

7.3.3.2 PGA Gain Plots

The PGA has an 8-bit resolution with a gain range of –3 dB to 18 dB. Figure 23 below shows a plot for the gain.

Each channel has a independent PGA controlled by registers CH1 PGA and CH2 PGA, and programmable

through the serial interface.

Figure 23. PGA Gain vs PGA Gain Code

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