ADR6

Bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

I

2

C SLAVE address (chip address)

SDA

SCL

S

P

START condition

STO

P condition

LP3958

www.ti.com

SNVS423C – JANUARY 2006 – REVISED MARCH 2013

I2C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.

The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I2C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

Figure 23. I2C Start and Stop Conditions

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been

addressed must generate an acknowledge after each byte has been received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). The LP3958 address is 59H (101 1001b). For the eighth bit, a “0”

indicates a WRITE and a “1” indicates a READ. This means that the first byte is B2H for WRITE and B3H for

READ. The second byte selects the register to which the data will be written. The third byte contains data to write

to the selected register.

Figure 24. I2C Chip Address

Register changes take an effect at the SCL rising edge during the last ACK from slave.

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