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LP8900TLE-AAEB 数据表(PDF) 13 Page - Texas Instruments |
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LP8900TLE-AAEB 数据表(HTML) 13 Page - Texas Instruments |
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13 / 23 page ![]() 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) 0402, 6.3V, X5R 0603, 10V, X5R 100 80 60 40 20 13 LP8900 www.ti.com SNVS542E – MAY 2008 – REVISED JUNE 2016 Product Folder Links: LP8900 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Other ceramic types such as Y5V and Z5U are less suitable owing to their inferior temperature characteristics. (See Capacitor Characteristics.) It is also recommended that the output capacitor is placed within 1 cm of the output pin and returned to a clean, low impedance, ground connection. It is possible to use tantalum or film capacitors at the device output, OUT, but these are not as attractive for reasons of size and cost. (See Capacitor Characteristics.) 9.2.2.4 No-Load Stability The LP8900 remains stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications. 9.2.2.5 Capacitor Characteristics The LP8900 is designed to work with ceramic capacitors on the input and outputs to take advantage of the benefits they offer. For capacitance values around 1 µF, ceramic capacitors give the circuit designer the best design options in terms of low cost and minimal area. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly dependant on the conditions of operation and capacitor type. In particular, to ensure stability, the output capacitor selection must take account of all the capacitor parameters, to ensure that the specification is met within the application. Capacitance value can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values may also show some decrease over time due to aging. The capacitor parameters are also dependant on the particular case size with smaller sizes giving poorer performance figures in general. Figure 12. Effect of DC Bias on Capacitance Value As an example Figure 12 shows a typical graph showing a comparison of capacitor case sizes in a capacitance vs. DC bias plot. As shown in Figure 12, as a result of the DC bias condition, the capacitance value may drop below the minimum capacitance value given in Table 2. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions as some capacitor sizes (for example, 0402) may not be suitable in the actual application. Ceramic capacitors have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 4.7-µF ceramic capacitor is in the range of 20 m Ω to 40 mΩ, which easily meets the ESR requirement for stability for the LP8900. The temperature performance of ceramic capacitors varies by type. Capacitor type X7R is specified with a tolerance of ±15% over the temperature range –55°C to +125°C. The X5R has a similar tolerance over the reduced temperature range of –55°C to +85°C. Some large value ceramic capacitors (4.7 µF) are manufactured with Z5U or Y5V temperature characteristics, which can result in the capacitance dropping by more than 50% as the temperature varies from 25°C to 85°C. Therefore, X7R or X5R types are recommended in applications where the temperature changes significantly above or below 25°C. |
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