STM32F412RGU7P datasheet(38/201 Pages) STMICROELECTRONICS

38 / 201 page

Functional overview

STM32F412xE/G

38/201

DocID028087 Rev 7

3.27

Inter-integrated sound (I2S)

Five standard I2S interfaces (multiplexed with SPI1 to SPI5) are available. They can be

operated in master or slave mode, in simplex communication mode, and full duplex mode

for I2S2 and I2S3. All I2S interfaces can be configured to operate with a 16-/32-bit resolution

as an input or output channel. I2Sx audio sampling frequencies from 8 kHz up to 192 kHz

are supported. When either or both of the I2S interfaces is/are configured in master mode,

the master clock can be output to the external DAC/CODEC at 256 times the sampling

frequency.

All I2Sx interfaces can be served by the DMA controller.

3.28

Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S applications. It allows to

achieve error-free I2S sampling clock accuracy without compromising on the CPU

performance, while using USB peripherals.

Different sources can be selected for the I2S master clock of the APB1 and the I2S master

clock of the APB2. This gives the flexibility to work with two different audio sampling

frequencies. The different possible sources are the main PLL, the PLLI2S, HSE or HSI

clocks or an external clock provided through a pin (external PLL or Codec output)

The PLLI2S configuration can be modified to manage an I2S sample rate change without

disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging

from 8 KHz to 192 KHz.

3.29

Digital filter for sigma-delta modulators (DFSDM)

The device embeds one DFSDM with 2 digital filters modules and 4 external input serial

channels (transceivers) or alternately 2 internal parallel inputs support.

The amount of filters defines the number of conversions which can be performed

simultaneously.

The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to

microcontroller and then to perform digital filtering of the received data streams (which

represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse

Density Modulation) microphones and perform PDM to PCM conversion and filtering in

hardware. DFSDM features optional parallel data stream inputs from microcontrollers

memory (through DMA/CPU transfers into DFSDM).

DFSDM transceivers support several serial interface formats (to support various Σ∆

modulators). DFSDM digital filter modules perform digital processing according user

selected filter parameters with up to 24-bit final ADC resolution.

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